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MP86961 20a, 27v intelli-phase tm solution (integrated hs/ls fets and driver) in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 1 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the MP86961 is a monolithic half bridge with built-in internal power mosfets and gate driver. it achieves 20a continuous output current over a wide input supply range. integrating the driver and mosfets results in high efficiency due to optimal dead time control and parasitic inductance reduction. the MP86961 is a monolithic ic designed to drive up to 20a per phase. housed in a very small 5x5mm qfn packge, this device can be operated from 100khz to 1mhz. the ic is intended to work with 5v tri-state output controllers. the MP86961 is ideal for notebook applications where efficiency and small size are a premium. features ? wide 4.5v to 21v operating input range ? 20a output current ? simple logic interface(5.0v) ? operate from 100khz to 1mhz ? accepts 3-state pwm input ? suitable for single-/multi-phase operation ? available in a 5mm x 5mm qfn package ? rohs6 compliant applications ? power modules ? notebook, core voltage ? graphic card core regulators all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithi c power systems, inc. this product is patent pending. typical application en in bst sw vcc pg gnd pwm sync agnd MP86961 4 6 5 3 10-18 2 8 7 9 l c in v in 4.5v-21v on/off c out v out 0.8v to 1.2v @ 20a c6 100nf cs 1 f 16v v cc 5v efficiency (%) output current (a) 50 55 60 65 70 75 80 85 90 95 100 02468101214161820 v in =12v v out =1.2v
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 2 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking free air temperature(t a ) MP86961du 5x5 qfn 86961du -40 c to +85 c * for tape & reel, add suffix ?z (e.g. MP86961du?z); for rohs compliant packaging, add suffix ?lf (e.g. MP86961du?lf?z) package reference exposed pad connect to pin pin 1 id gnd gnd gnd gnd gnd gnd gnd gnd gnd n/c vcc en sync pwm pg bst in agnd 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 gnd gnd gnd gnd sw in in in in sw sw sw absolute maxi mum ratings (1) supply voltage v in ....................................... 27v v sw???????????????.. -0.3v (-3v for <20ns) ????????.to v in + 0.3v (+3v for <20ns) v bst ...................................................... v sw + 6v all other pins ..................................-0.3v to +6v continuous power dissipation (t a = +25c) (2) ............................................................. 3.5w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.5v to 21v v cc driver voltage ???????4.5v to 5.5v operating junct. temp (t j )...... -40 c to +125 c thermal resistance (4) ja jc 5x5 qfn ................................. 36 ....... 8.... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on approximately 4? square of 4-layer pcb.
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 3 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units i cc standby i cc_stdby v cc =5v, pwm=en=lo 230 300 a i in (shutdown) i in (off) v cc = 0v 1 5 a i in standby i in_stdby v cc =5v, pwm=en=lo 1 a rise time i out = 20a 5 ns fall time i out = 20a 3 ns minimum on-time 55 ns dead-time rising 5 ns dead-time falling 10 ns v cc under voltage lockout threshold rising 3.7 4.2 v v cc under voltage lockout threshold hysteresis 470 mv sync pull-up current i sync sync=0v -14 a sync logic high voltage 2 v sync logic low voltage 0.4 v en input low voltage 0.4 v en input high voltage 2 v power good rds(on) en=0v 20 ? pwm input v pwm =5v 90 a input current i pwm v pwm =0v -90 a pwm low to tri-state rising threshold 1.7 v pwm tri-state to high threshold 3.7 v pwm high to tri-state rising threshold 3.4 v pwm tri-state to low threshold 1 v tri-state shutdown holdoff time t tsshd v cc =5v, temperature=25c 80 ns ug/lg three-state propagation delay t pts 20 ns usw turn-off propagation delay t pdul v cc =5v 30 ns lsw turn-off propagation delay t pdll v cc =5v 10 ns usw turn-on propagation delay t pduh v cc =5v 20 ns lsw turn-on propagation delay t pdlh v cc =5v 45 ns
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.21 www.monolithicpower.com 4 12/26/2013 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. t pduh t pdll 0v sw pwm v out t pdul t pdlh t tsshd figure 1- timing diagram pin functions pin # name description 1 nc not connected. 2 vcc low-side driver bias supply. de couple with a 1f ceramic capacitor. 3 agnd signal ground. 4 en active high on/off control. pulling this pin low forces the sw pin to be in a high impedance state. 5 sync leaving this pin open enables the lower sy nchronous switch. pulling it low forces the lower switch into diode emulation mode. 6 pwm pulse width modulation control. accepts thr ee state input. force pwm to midstate or open to place sw into high impedance state. 7 pg power good. open drain output is low impedance to ground until internal supplies are good. 8 bst bootstrap. this capacitor is needed to driv e the power switch?s gate above the supply voltage. it is connected between sw and bst pins to form a floating supply across the power switch driver. 9 exposed pad in supply voltage. c in is needed to prevent large voltage spikes from appearing at the input. 10?18 exposed pad gnd power ground. exposed pad sw switch output. t hese pins are fused together.
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 5 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in = 12v, v cc = 5v, v out = 1.2v, t a = +25oc, unless otherwise noted. efficiency (%) efficiency (%) output current (a) output current (a) output current (a) efficiency (%) output current (a) 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 power loss (w) power loss (w) power loss (w) power loss (w) output current (a) power loss (w) output current (a) power loss (w) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 300 400 500 600 700 800 900 1000 switching frequency (khz) 0 0.5 1 1.5 2 3 3.5 4 8 101214161820 input voltage (v) 0 1 2 2.5 3 4 8 101214161820 1.9 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 2.35 0.8 1 1.2 1.4 1.6 1.8 2 2.2 output voltage (v) 20a 15a 300khz 600khz 1.0mhz i out =15a, fsw=600khz i out =15a 50 55 60 65 70 75 80 85 90 95 100 02468101214161820 50 55 60 65 70 75 80 85 90 95 100 0 2 4 6 8 101214161820 50 55 60 65 70 75 80 85 90 95 100 02468101214161820
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 6 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v cc = 5v, v out = 1.2v, t a = +25oc, unless otherwise noted. temperature rise vs. output current no airflow v sw 500mv/div. sw rising edge dead time i out = 15a v sw 1v/div. sw falling edge dead time i out = 15a v sw 5v/div. output waveform i out = 20a v sw 10v/div. v out 1v/div. i out 25a/div. soa waveform v in = 19v, v out = 1.2v i out = 20 to 80a, f sw = 600khz 0 10 20 30 40 50 60 70 0 5 10 15 20 output current (a) case temperature rise ( o c) 300khz 600khz
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 7 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. efficiency measurement setup
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 8 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram hgate en v out lgate tri-state pwm sync m2 sw in bst gnd v cc pwm pwm logic lgate diode emulation logic en v cc v cc v bst pg tsd vcc vcc 150 50 50 en en figure 2?functional block diagram
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 9 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation the MP86961 is a 20a monolithic half bridge driver with mosfets ideally suited for single- /multi-phase buck regulators. once the en, v in , v cc and v bst signals are sufficiently high, operation begins. bst voltage has a typical rising uvlo of 2.2v and a falling uvlo of 2.0v. when bst is below the uvlo voltage, the device will be off. MP86961 can work with most pwm controllers. the device accepts pwm signal from 100khz up to 1mhz. there is an internal resistor divider to put pwm voltage to tri-state region if the pwm pin is open. internally, sync is tied to v cc through a resistor. by default, the device will operate in synchronous mode. to enter diode emulation mode, drive sync pin low. startup and shutdown sequence MP86961 can work with any startup or shutdown sequencing combination of v in , v cc and en. if pwm signal is present, the MP86961 will start working whenever v in , v cc and en are ready. on the other hand, if any of these signals is not ready, the MP86961 will stop working. however, it is recommended to turn on and turn off the device through the en pin. pcb layout guideline pcb layout is very important to achieve stable operation. please follow these guidelines to achieve optimal performance. 1) keep the path of switching current short and minimize the loop area formed by input capacitor. keep the connection between sw pin and input power ground as short and wide as possible. 2) always place some input bypass ceramic capacitors next to the device and on the same layer as the device. do not put all of the input bypass capacitors on the back side of the device. use as many vias and input voltage planes as possible to reduce the switching spike. bst capacitor and v cc capacitor should also be as close to the device as possible. 3) the recommended external bst cap is 100nf. do not use a capacitance value lower than 100nf. place a 1.0 ? resistor between the bst capacitor and bst pin for optimized performance. 4) do not place via on the pad or on the pin footprint. doing so may cause soldering issue during the assembling process. use figure 3 as a via placement reference. 5) connect in, sw and gnd to large copper area and use vias to cool the chip to improve thermal performance and long-term reliability. see figure 4 as an example. figure 3?via placement guideline do not put via on the device?s pad footprint or pin footprint to avoid assembly issue. use as many vias as possible to cool down the device. 6) place the v cc decouple capacitor close to the ic. connect agnd and pgnd at the point of v cc capacitor's ground connection. recommended smt setting stencil thickness: 0.12mm ep pad opening: (stencil opening : real pcb size) length: 0.85:1 width: 1:1 note: the ep pad for intelli-phase are in, sw and gnd pad on the bottom. solder type: #3
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn MP86961 rev. 1.22 www.monolithicpower.com 10 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 4?copper area guideline use large copper area, many vias and many in, sw and gnd inner layer planes to achieve optimal thermal performance. input capacitors output capacitors inductor intelli phase (vin plane) (gnd plane) (sw plane) c v cc r bst c bst
MP86961 ?20a, 27v intelli-phase solution integrated hs/ls fets and driver in a 5x5mm qfn notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP86961 rev. 1.22 www.monolithicpower.com 11 12/26/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information fctqfn18l (exposed pad) side view top view 1 10 9 bottom view 4.90 5.10 4.90 5.10 0.50 bsc 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking recommended land pattern note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference is mo-229, variation vjjd. 5) drawing is not to scale. pin 1 id see detail a pin 1 id option b r0.20 typ. pin 1 id option a 0.20x45 ? typ. detail a pin 1 id index area 18 9 0.30 0.40 0.50 1.50 0.70 0.18 0.30 0.59 bsc 1.77 bsc 4.13 bsc 2.95 bsc 1.30 1.50 2.80 bsc 0.40 0.60 0.50 0.70 0.40 0.60 0.25 2.80 4.90 0.60 0.70 0.60 0.59 1.77 2.95 4.13

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